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Silicon Labs /EFR32MG21A020F1024IM32 /GPIO_S /TIMER0_ROUTEEN

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Interpret as TIMER0_ROUTEEN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CC0PEN)CC0PEN 0 (CC1PEN)CC1PEN 0 (CC2PEN)CC2PEN 0 (CDTI0PEN)CDTI0PEN 0 (CDTI1PEN)CDTI1PEN 0 (CDTI2PEN)CDTI2PEN

Description

No Description

Fields

CC0PEN

CC0 pin enable control bit
CC1PEN

CC1 pin enable control bit
CC2PEN

CC2 pin enable control bit
CDTI0PEN

CDTI0 pin enable control bit
CDTI1PEN

CDTI1 pin enable control bit
CDTI2PEN

CDTI2 pin enable control bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data